## Delay calculation using Logical Effort (both static and Pseudo)

Design an unit inverter with 2X fanout. Measure the propagagtion delay. Keep this delay as the reference.

Write down the last two digits of your roll number using an 8-bit format (first four bits to represnt the first number and second four bits to represent the second number : for eg; 23 is 0010 0011). Multiply this number using the 8-bit representation of (255 - roll no). For eg with the roll no as 23, the multiplicand would be 255-23 = 232 = 11101000. the product would be of 16 bits (leave the overflow if any). Count the number of ones and zeros in the product. Plug this product in to a 4 bit Karnaugh Map as per the position. For example the product is 1111000011111110 then the K-map looks like the one shown below. If the number of 1's greater than number of 0's then take SOP else take POS. You will get a boolean expression of four bits. Assume you don't have complementary inputs. Implement the boolean function only by using NOT, 2-input NAND and NOR gates. Assume this boolean function drives a capacitance of (roll no multiplied by 1000) fF. Calculate the delay through all the paths using Logical effort, findout the critical path and resize the gates for optimum delay :) .

Implement the entire setup in Cadence and calculate the delay.

The submission should have all the calculations, cadence plots (with white background and visible).