Design of a single stage amplifier

1. Design a single stage amplifier(with resistive load, diode connected and active-PMOS) with gain as 20 dB and UGB 1GHz. Use a load capacitance of 0.1pF. Measure the Gain, 3 dB BW, UGB, slew rate, voltage swing.

2. On paper, derive the high frequency gain for single stage amplifier (with active-PMOS). Identify the zeros and poles, relate the poles and zeros to the corresponding capacitors.